GB/T 14139-2019Silicon epitaxial wafers (English PDF)

Foreword

This standard was drafted in accordance with the rules given in GB/T 1.1-2009.

This standard replaces GB/T 14139-2009 "silicon epitaxial wafer". This standard is compared with GB/T 14139-2009, except for editorial changes. The main technical changes are as follows.

--- Revised the scope of application, "This standard applies to n-type epitaxial layers (N/N) grown on N-type silicon polished wafer substrates and at p A homogenous silicon epitaxial wafer of a P-type epitaxial layer (P/P) grown on a silicon-polished substrate. Products are mainly used to make silicon semiconductors Device. Other types of silicon epitaxial wafers can be referred to. "" This standard applies to N-types with a diameter of not more than 150mm. And silicon epitaxial wafers grown on P-type silicon polished wafer substrates (see Chapter 1, Chapter 1 of the 2009 edition).

--- GB/T 12962, GB/T 14145, YS/T 24 have been deleted from the normative reference documents, and GB/T 1550 has been added. GB/T 1555, GB/T 14844, GB/T 19921, GB/T 24578, YS/T 28, SEMIM85 (see Chapter 2, 2009) Chapter 2 of the annual edition).

--- Added "terms and definitions" (see Chapter 3).

--- List the product's grades and classifications separately, and revised the orientation of the grades and the crystal orientation of the epitaxial layer (see Chapter 4, 2009 edition) 3.1).

--- Revised the requirements for substrate materials for epitaxial wafers (see 5.1, 3.2 of 2009 edition).

--- Increased the conductivity type, crystal orientation requirements, test methods, inspection rules, etc. of the epitaxial layer (see 5.2.1, 5.2.2, 6.1, 6.2, 7) chapter).

--- Epitaxial layer resistivity is revised from the central resistivity to the average resistivity, and the resistivity, resistivity allowable deviation and radial resistance are revised. Rate change requirements (see 5.2.3, 2009 edition 3.3).

---The thickness of the epitaxial layer is revised from the center thickness to the average thickness, and the requirements for thickness, thickness tolerance and radial thickness variation are revised. (See 5.2.4, 3.4 of the 2009 edition).

--- Increased the vertical resistivity distribution of the epitaxial layer and the transition zone width requirements, test methods, inspection rules, etc. (see 5.2.5, 6.5, 7) chapter).

--- Revised the requirements for the dislocation density of the epitaxial layer, revised from "not more than 500/cm2" to "should be no more than 50cm-2" (see 5.2.6, 3.5.1 of the 2009 edition).

--- Increased surface metal requirements, test methods and inspection rules (see 5.2.7, 6.7, Chapter 7).

--- Removed the requirement for large defects (see 3.6.1 of the 2009 edition).

--- Removed "surface defect area refers to the silicon epitaxial wafer with a diameter of not more than 76.2mm to remove the edge 2mm annular area, diameter 100mm, 125mm and 150mm silicon epitaxial wafers remove the entire surface of the 3mm annular region of the edge" (see 2009 edition) 3.6.2).

--- Removed "surface spot defects including nails, adhering particles, protrusions, inclusions, hillocks and pyramids in accordance with GB/T 14264. Particles that can be removed using cleaning techniques are not point defects (see 3.6.3 of the 2009 edition).

--- Removed "Blinding" means that the edge of the epitaxial wafer has a defect depth greater than 0.3 mm in the radial direction. The maximum chipping radial depth is not More than 0.5mm, the maximum perimeter length of the cumulative collapse is no more than 2.5mm" (see 3.6.4 of the 2009 edition).

--- Removed the definition of "fog see GB/T 14264" (see 3.6.5 of the 2009 edition).

--- Removed "stains including stains, gloves, dust, smudges and solvent residues" (see 3.6.6 for the 2009 edition).

--- Increased the requirements for group approval and inspection items (see 7.2, 7.3).

---Modified packaging requirements (see 8.1.1, 6.1.1 of the 2009 edition).

--- Added order form (or contract) content (see Chapter 9).

This standard is supported by the National Semiconductor Equipment and Materials Standardization Technical Committee (SAC/TC203) and National Semiconductor Equipment and Materials Standards. The Technical Committee of Materials Technical Committee (SAC/TC203/SC2) jointly proposed and managed.

1 Scope

This standard specifies the grade and classification, requirements, test methods, inspection rules, marking, packaging, transportation, storage, quality certification of silicon epitaxial wafers. Book and order form (or contract) content.

This standard applies to silicon epitaxial wafers grown on N-type and P-type silicon polishing pad substrates with a diameter of not more than 150 mm.

2 Normative references

The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this document. For undated references, the latest edition (including all amendments) applies to this document.

GB/T 1550 Test method for conductivity type of extrinsic semiconductor materials

GB/T 1555 semiconductor single crystal orientation determination method

GB/T 2828.1-2012. Sampling procedures for counting sampling - Part 1. Quantitative inspection by batches plan

GB/T 6617 silicon resistivity measurement extended resistance probe method

GB/T 6624 silicon polishing sheet surface quality visual inspection method

GB/T 12964 silicon single crystal polishing sheet

GB/T 13389 boron-doped phosphorus-doped arsenic-doped silicon single crystal resistivity and dopant concentration conversion procedure

GB/T 14141 Determination of thin layer resistance of silicon epitaxial layers, expanded layers and ion implantation layers - Inline four-probe method

GB/T 14142 silicon epitaxial layer crystal integrity test method corrosion method

GB/T 14146 silicon epitaxial layer carrier concentration determination mercury probe capacitance-voltage method

GB/T 14264 semiconductor material terminology

GB/T 14844 semiconductor material grade representation

Infrared reflection measurement method for thickness of lightly doped silicon epitaxial layer on heavily doped substrate of GB/T 14847

GB/T 19921 Silicon polishing sheet surface particle test method

GB/T 24578 Total reflection X-ray fluorescence spectrometry method for metal contamination on silicon wafer surface

YS/T 28 wafer packaging

SEMIM85 Guide for the determination of trace metal contamination on silicon wafers. Inductively coupled plasma mass spectrometry (Guideforthemeas- Urementoftracemetalcontaminationonsiliconwafersurfacebyinductivelycoupledplasmamass Spectrometry)

3 Terms and definitions

The following terms and definitions as defined in GB/T 14264 apply to this document.