GB/T 35010.3-2018Semiconductor die products—Part 3: Guide for handling, packing and storage (English PDF)
半导体芯片产品 第3部分：操作、包装和贮存指南
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Issued by
SAMR; SAC
Level / Type
National · Recommended
Issue date
March 15, 2018
Implementation date
August 1, 2018
Scope
GB/T 35010.3-2018 is the English-translated version of 半导体芯片产品 第3部分：操作、包装和贮存指南.
GB/T 35010.3-2018 is the part of the Chinese semiconductor die products series that gives guidance on how dies and wafers are handled, packed and stored. It covers wafers, single bare dies, dies and wafers with interconnect structures, and minimally or partially packaged dies and wafers.
The guidance runs from handling rules, work environment control and clean areas through wafer thinning, dicing and die sorting, to wafer carriers and boxes, single-wafer, die tray and die carrier packing, thin die products, secondary packing for transport and recycling of packing materials.
It also deals with short-term and long-term storage and with the traceability of wafers and dies, and asks for tools and containers that meet the electrostatic protection requirements of IEC 61340-5-1 and IEC 61340-5-2. It was issued on 15 March 2018 and has applied since 1 August 2018.
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Document preview — GB/T 35010.3-2018
National Standard of the People's Republic of China
- ICS
- 31.200
- Classification
- L 55
Issued by: State Administration for Market Regulation; Standardization Administration of the PRC
Contents
- Preface
- 1 Scope
- 2 Normative references
- 3 Terms and Definitions
- 4 Operation
- 4.1 General rule
- 4.2 Work Environment Control
- 4.3 General Notes
- 4.4 Clean Area
- 5 Process Operation
- 5.1 Wafer Thinning
- 5.2 Wafer Dicing
- 5.3 Chip Sorting Process
- 6 Transfer, Storage and Packaging of Chip Products
- 6.1 General Clause
- 6.2 Wafer Carriers and Wafer Boxes
- 6.3 Wafer Online Storage and Transmission
- 6.4 Packaging without Open Wafers
- 6.5 Wrapped wafers
- 6.6 Single Wafer Packaging
- 6.7 Chip Tray (Box) Packaging
- 6.8 Chip Carrier Packaging
- 6.9 Handling and Packaging of Thin Chip Products
- 6.10 Secondary packaging during transport
- 6.11 Recycling of packaging materials
- 7 Short-term and long-term storage of chip products
- 7.1 General
- 7.2 Short-term storage of chip products
- 7.3 Long-term storage of chip products
- 8 Traceability
- 8.1 General Rule
- 8.2 Wafer traceability
- 8.3 Traceability of Chips
- 8.4 The back of the chip product identifies
- Appendix A (Informative) Schedule Checklist
Foreword
GB/T 35010 "Semiconductor Chip Products" is divided into the following parts.
--- Part 1. Procurement and use requirements;
--- Part 2. Data exchange format;
--- Part 3. Guidelines for handling, packaging and storage;
--- Part 4. Chip user and supplier requirements;
--- Part 5. Electrical Simulation Requirements;
--- Part 6. Thermal Simulation Requirements;
--- Part 7. XML format for data exchange;
--- Part 8. EXPRESS format for data exchange.
This part is Part 3 of GB/T 35010.
This section was drafted in accordance with the rules given in GB/T 1.1-2009.
1 Scope
This part of GB/T 35010 gives general requirements for the operation, packaging and storage of semiconductor chip products.
This section applies to the operation, packaging, storage and use of semiconductor chip products (hereinafter referred to as chip products). The semiconductor chip products referred to in this section include.
--- Wafers;
---Single bare chip;
--- Chips and wafers with interconnect structures;
---Minimum or partially packaged chips and wafers.
2 Normative references
The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this document. For undated references, the latest version (including all amendments) applies to this document.
GB/T 2900 (all parts) Electrical terminology
GB/T 25915.1-2010 Cleanrooms and related controlled environments - Part 1. Air cleanliness class
GB/T 35010.1-2018 Semiconductor chip products Part 1. Procurement and use requirements
IEC 61340-5-1 Electrostatics-Section 5-1. General requirements for electrostatic protection of electronic devices (Electrostatics-Part 5-1. Protectionofelectronicdevicesfrom electrostaticphenomena-Generalrequirements)
IEC 61340-5-2 Electrostatics - Part 5-2. Electrostatic Protection User Guide for Electronic Devices (Electrostatics-Part 5-2. Protectionofelectronicdevicesfromelectrostaticphenomena-Userguide)
3 Terms and definitions
The terms and definitions defined in GB/T 2900 (all parts) and GB/T 35010.1-2018 apply to this document.
4 Operation
4.1 General rules
During the operation of the chip product, special tools should be used to avoid contact with the bare active surface of the chip product; when the contact is inevitable When free, special tools and materials should be used.
The tools, materials and storage containers used during the operation and delivery of the chip products shall comply with the corresponding anti-static requirements (see IEC 61340-5-1, IEC 61340-5-2).
During the operation of the chip product, attention should be paid to the sensitivity of the chip to specific chemical substances. Recommendations See Appendix A for an example planning checklist.
4.2 Work Environment Control
The typical process environmental conditions for general-purpose semiconductor processes (excluding the storage of chip products) are as follows. […]
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This preview omits tables, figures, formulas and parts of the technical clauses. The complete document — 24 pages — is available in the English PDF.
Referenced standards
Normative references
- GB/T 25915.1-2010Cleanrooms and associated controlled environments - Part 1: Classification of air cleanliness by particle concentration
- GB/T 35010.1-2018Semiconductor die products -- Part 1: Requirements for procurement and use
GB/T 2900 · IEC 61340-5-1 · IEC 61340-5-2
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