GB/T 15877-2013Semiconductor integrated circuits -- Specification of DIP lead frames produced by etching (English PDF)

Foreword

This standard was drafted in accordance with the rules given in GB/T 1.1-2009.

This standard replaces GB/T 15877-1995 "etched double-row package lead frame specification". Compared with GB/T 15877-1995 the technical changes are as follows.

---About Chapter 2 Normative References. Sampling Standards Replace SJ/Z9007-1987 by GB/T 2828.1-2012, GB/T 14112-1993 was changed to GB/T 14112-2015; additional reference documents GB/T 2423.60-2008, SJ20129;

--- Chapter 3 adds the terms and definitions of nominal length, side erosion, surface corrosion, and chip bonding area sag;

---4.1 lead frame size, the minimum area of the wire bonding area, the spacing between the metal;

---4.2 lead frame shape and position tolerance, delete the relevant content of the co-planarity of the coining zone, the depth of the coining zone, and increase the insulation Requirements for gaps, chip bonding areas, and internal position tolerances of lead frames;

---Modified the requirements of "side bend". the original standard is stipulated according to the nominal length, this standard stipulates that the side bend does not exceed 0.051mm;

--- Modified the "curl" requirements. the original standard only specifies that the curl deformation is less than 0.3% of the nominal strip length, this standard is based on the material Thickness is specified;

---Modified the requirements of "cross-bend". the original standard is stipulated according to the number of leads and the number of strips. This standard is stipulated according to the nominal length;

---Modified the requirements of "strip distortion". only the frame distortion is less than 0.5mm in the original standard, this standard will modify the frame distortion Distort the strip and specify it according to the thickness of the material;

--- Modified the "lead twist" requirements. the original standard only specifies that the lead twist is not more than 0.01mm, this standard specifies the lead twist not more than 3°30';

---Modified the requirements of "slice of chip bonding area". the original standard specifies the slope under pressure and pressure, this standard One is specified to have a maximum inclination of 0.05 mm per length of 2.54 mm in length or width;

---Modified the requirements of "flatness of chip bonding area". This standard modifies the flatness of the bonding area of the chip to the flatness of the bonding area of the chip.

The standard is stipulated according to the number of leads. This standard is uniformly specified to be 0.127mm from each side, and the flatness is not more than 0.005mm;

--- Adjusted the corresponding terms in the appearance of the 4.3 lead frame, adding burrs, pits, indentations, scratches, side etching and surface corrosion Relevant requirements;

---Modified the requirements of "local gold plating". the original standard specifies that the thickness of the gold plating layer is not less than 1.0µm, and the standard is modified to be not less than 0.7µm;

--- Revised the requirement of "local silver plating". the thickness of the silver plating layer specified in the original standard is not less than 3.8µm, and the standard is modified to be not less than 3µm;

--- Revised the "coating appearance" requirements. on the basis of the original standard, increased the relevant requirements for the appearance of the coating;

--- Increased the relevant requirements of the "copper stripping test";

--- Increased the relevant requirements of the "silver stripping test";

--- Added the relevant requirements of the "Appraisal Approval Process";

--- Revised the requirements of "inspection requirements". the original standard adopts a one-time inspection method, and this standard modifies the quality consistency test.

The composition of the test items of Group A, Group B and Group C; the sampling plan in the "Inspection Requirements" was revised;

--- Revised the relevant requirements of "storage". the original standard silver-plated lead frame has a shelf life of three months, and this standard specifies six months.

This standard was proposed by the Ministry of Industry and Information Technology of the People's Republic of China.

This standard is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee (SAC/TC78).

This standard was drafted. Ningbo Dongsheng Integrated Circuit Components Co., Ltd.

Drafters of this standard. Ren Zhongping, Yin Guoqin.

The previous versions of the standards replaced by this standard are.

---GB/T 15877-1995.

Semiconductor integrated circuit Etched double row package lead frame specification

1 Scope

This standard specifies the technical requirements and test methods for semiconductor integrated circuit etched double-row package lead frames (hereinafter referred to as lead frames).

Law and inspection rules.

This standard applies to semiconductor integrated circuit etched double-row (DIP) package lead frame (gold-plated and silver-plated), single-row etched lead frame the frame can also be used as reference.

2 Normative references

The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this article.

Pieces. For undated references, the latest edition (including all amendments) applies to this document.

GB/T 2423.60-2008 Environmental testing of electric and electronic products - Part 2. Test methods Test U. Terminals and overall Assembly strength GB/T 2828.1-2012.Sampling procedures for counting sampling - Part 1. Quantitative inspection by batches plan GB/T 7092 semiconductor integrated circuit dimensions GB/T 14112-2015 Specification for semiconductor integrated circuit plastic double-row package stamped lead frame GB/T 14113 semiconductor integrated circuit package terminology SJ20129 Metal plating thickness measurement method

3 Terms and definitions

The following terms and definitions as defined in GB/T 14113 apply to this document.

Nominal length

The length of the strip specified on the lead frame drawing.

Lateral erosion etchingonside the etching of the sidewalls of the wires under the resist pattern occurs (see Figure 1).

figure 1