GB/T 35007-2018Semiconductor integrated circuits—Measuring method of low voltage differential signaling circuitry (English PDF)
半导体集成电路 低电压差分信号电路测试方法
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Issued by
SAMR; SAC
Level / Type
National · Recommended
Issue date
March 15, 2018
Implementation date
August 1, 2018
Scope
GB/T 35007-2018 is the English-translated version of 半导体集成电路 低电压差分信号电路测试方法.
GB/T 35007-2018 sets out how to test low voltage differential signaling (LVDS) circuits in semiconductor integrated circuits.
It gives the test environment requirements and precautions, then the static parameter tests, from input threshold voltages, input currents and LVDS output high and low voltages to common-mode and differential output voltages, output short-circuit and leakage currents, built-in differential resistances and supply currents.
The dynamic tests cover input and output capacitance, dynamic supply current, maximum and minimum operating frequency, maximum data rate, transmission delays, transition times, pulse skew, channel-to-channel skew, eye height and width, and deterministic, random and total jitter.
An informative annex lists the requirements for the eye diagram test instrument. It was issued on 15 March 2018 and has applied since 1 August 2018.
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Document preview — GB/T 35007-2018
National Standard of the People's Republic of China
- ICS
- 31.200
- Classification
- L 56
Issued by: State Administration for Market Regulation; Standardization Administration of the PRC
Contents
- Preface
- 1 Scope
- 2 Normative references
- 3 Terms and Definitions
- 4 General
- 4.1 Test Environment Requirements
- 4.2 Test Considerations
- 5 Static Parameter Test
- 5.1 Single-Ended Digital Interface Parameters
- 5.2 Input High-Level Threshold Voltage (VTH)
- 5.3 Input Low-Level Threshold Voltage (VTL)
- 5.4 Input Current (IIN)
- 5.5 Power Supply Shutdown Input Current (IIN-OFF)
- 5.6 Output LVDS High Voltage (VOHL)
- 5.7 Output LVDS Low Voltage (VOLL)
- 5.8 Common Mode Output Voltage (VOS)
- 5.9 Compatible Common-Mode Output Voltage Variation (deltaVOS)
- 5.10 Differential Output Voltage (VOD)
- 5.11 Complementary Differential Output Voltage Variation (deltaVOD)
- 5.12 LVDS Output Short-Circuit Current (IOSL)
- 5.13 Power Off Output Leakage Current (IO-OFF)
- 5.14 LVDS Output High Impedance Current (IOZL)
- 5.15 Built-in Differential Input Resistance (RIT)
- 5.16 Built-in Differential Output Resistance (ROT)
- 5.17 Static Supply Current (IDD)
- 5.18 Turning Off the Supply Current (IDDZ)
- 6 Dynamic Parameter Test
- 6.1 Input Capacitor (CI) and Output Capacitor (CO)
- 6.2 Dynamic Supply Current (IDDA)
- 6.3 Maximum operating frequency (fMAX)
- 6.4 Minimum operating frequency (fMIN)
- 6.5 Maximum Data Rate (DRMAX)
- 6.6 Output from Low Level to High Level Transmission Delay (tPLH)
- 6.7 Output High to Low Transmission Delay (tPHL)
- 6.8 Output Transmission Delay from High-Z to High-Level (tPZH)
- 6.9 Output from High Impedance to Low Transmission Delay (tPZL)
- 6.10 Output from High Level to High Impedance Transmission Delay (tPHZ)
- 6.11 Output from Low Level to High Impedance Transmission Delay (tPLZ)
- 6.12 Output Transition from Low Level to High Level (tTLH)
- 6.13 Output Transition from High Level to Low Level (tTHL)
- 6.14 Pulse Skew (tSKP)
- 6.15 Interchannel Time Lag (tSKO)
- 6.16 Eye height (eH)
- 6.17 Eye Width (eW)
- 6.18 Deterministic jitter (Dj)
- 6.19 Random Jitter (Rj)
- 6.20 Total Jitter
- Appendix A (Informative Appendix) Eye Diagram Test Instrument Requirements
Foreword
This standard was drafted in accordance with the provisions given in GB/T 1.1-2009.
1 Scope
This standard specifies a low voltage differential signaling (LVDS) circuit for semiconductor integrated circuits ( The basic principle of the static parameter and dynamic parameter test method is called "device".
This standard applies to the test of static parameters and dynamic parameters of low-voltage differential signal circuits.
2 Normative references
The following documents are indispensable for the application of this document. For dated references, only dated versions apply to this document. For undated references, the latest version (including all amendments) applies to this document.
GB/T 17574-1998 Semiconductor device integrated circuit Part 2. Digital integrated circuits
3 Terms and definitions
The following terms and definitions apply to this document.
3.1 Pulse skew
In the same channel, the transmission delay time from the low level to the high level and the transmission delay time from the high level to the low level are output. Difference.
3.2 Channel-to-channel skew
For multi-channel devices, the difference in transmission delay between different channels.
3.3 Eye diagram
The result of superimposing and displaying the bit stream of the collected serial signal is cumulatively accumulated in the afterglow manner, and the superimposed figure is an eyelet shape.
3.4 Eye height
The amplitude of the eye opening in the vertical direction.
3.5 Eye width
The amplitude of the eye opening in the horizontal direction.
3.6 Jitter
The short-term deviation of the signal at a certain moment relative to its ideal time position.
3.7 Deterministic jitter
Due to the identifiable interference signal, the amplitude of the jitter is limited and has non-random causes.
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This preview omits tables, figures, formulas and parts of the technical clauses. The complete document — 32 pages — is available in the English PDF.
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