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GB/T 44775-2024Integrated circuit 3D packaging—Requirement for die stack process and evaluation (English PDF)

集成电路三维封装芯片叠层工艺过程和评价要求

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Issued by

SAMR; SAC

Level / Type

National · Recommended

Issue date

October 26, 2024

Implementation date

May 1, 2025

Scope

GB/T 44775-2024 is the English-translated version of 集成电路三维封装芯片叠层工艺过程和评价要求.

GB/T 44775-2024 is the Chinese national standard covering the stacking of two or more active dies into one circuit — the bonders, ovens and cleaning machines, the room conditions and the check on the chips to be stacked, the wire bonding route and the flip chip route each taken step by step, the labelling, transport and records, and the evaluation set separately for the two routes, because a defect buried under the next die can no longer be reworked. Companion to the wafer thinning standard GB/T 44791-2024 and the wafer sawing standard GB/T 44796-2024. First edition, under the Ministry of Industry and Information Technology. In force from 1 May 2025. Issued on 26 October 2024, it has been in force since 1 May 2025.

Document preview — GB/T 44775-2024

National Standard of the People's Republic of China

ICS: 31.200
Classification: L 55

Issued by: State Administration for Market Regulation; Standardization Administration of the PRC

PrefaceIII
1 Scope1
2 Normative references1
3 Terms and Definitions1
4 General Requirements1
4.1 Equipment, instruments and fixtures1
4.2 Materials2
4.3 Note2
5 Detailed requirements2
5.1 Environment2
5.2 Typical process flow3
5.3 Process Preparation4
5.4 Confirmation of Chips to be Stacked5
5.5 Wire Bonding Chip Stacking Process5
5.6 Flip Chip Stacking Process7
5.7 Labeling, transportation and storage8
5.8 Record8
6 Evaluation Requirements8
6.1 Evaluation Requirements for Wire Bonding Chip Stacking Processes8
6.2 Evaluation requirements for flip chip stacking processes13

Foreword

This document is in accordance with the provisions of GB/T 1.1-2020 "Guidelines for standardization work Part 1: Structure and drafting rules for standardization documents" Drafting.

Please note that some of the contents of this document may involve patents. The issuing organization of this document does not assume the responsibility for identifying patents.

This document is proposed by the Ministry of Industry and Information Technology of the People's Republic of China.

This document is under the jurisdiction of the National Technical Committee for Standardization of Integrated Circuits (SAC/TC599).

This document was drafted by the 58th Research Institute of China Electronics Technology Group Corporation and Shenzhou Loongson Intelligent Technology Co., Ltd.

The main drafters of this document are Yuan Shiwei, Gao Nayan, Xiao Hanwu, Shuai Zhe, Huang Hailin, Xiao Longteng, and He Huiying.

Integrated circuit 3D packaging Chip stacking process and evaluation requirements

1 Scope

This document specifies the chip stacking process and evaluation using wire bonding and flip chip technology in integrated circuit 3D packaging. Require.

This document applies to circuits stacked using wire bonding and flip-chip processes in integrated circuit three-dimensional packaging.

2 Normative references

GB/T 25915.1-2021

GB/T 35005-2018

3 Terms and Definitions

The following terms and definitions apply to this document.

3.1 Chip stacking diestack

Horizontal integration of chips containing two or more layers of active electronic devices into a single circuit.

4 General requirements

4.1 Equipment, instruments and fixtures

The equipment and instruments required for the lamination process should be regularly identified and calibrated. The fixtures should be intact and clean, and the specifications and dimensions should be consistent with the process requirements.

In order to adapt to the requirements, the commonly used equipment, instruments and fixtures are shown in Table 1.

Table 1 Commonly used equipment, instruments and fixtures Serial No. Name Main Technical Requirements Application 1 Mounting machine chip accuracy. XY no more than 20µm, rotation less than or equal to 0.5° dispensing and mounting process 2 The temperature and pressure range of the hot press welder are adjustable for flip chip interconnection 3 The temperature error of the curing oven shall not exceed 10°C; the time error shall not exceed 5s within 30min.

4 Reflow oven temperature adjustable for solder paste welding and glue curing

5 No flux residue on the chip surface after cleaning by the cleaning machine. Cleaning the flip chip flux.

6 Low-power microscope meets the requirements for microscopic examination and appearance inspection after mounting

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This preview omits tables, figures, formulas and parts of the technical clauses. The complete document — 20 pages — is available in the English PDF.

Referenced standards

Normative references

GB/T 35005-2018Test methods for flip chip integrated circuits

GB/T 25915.1-2021

Editions of GB/T 44775

Edition	Title	Revision	Status
GB/T 44775-2024	Integrated circuit 3D packaging - Requirement for die stack process and evaluation	current edition	Current

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