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GB/T 33657-2017Nanotechnologies—Electrical operating parameter test specification of wafer level nano-scale phase change memory cells (English PDF)

纳米技术 晶圆级纳米尺度相变存储单元电学操作参数测试规范

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Issued by

SAMR; SAC

Level / Type

National · Recommended

Issue date

May 12, 2017

Implementation date

December 1, 2017

Scope

GB/T 33657-2017 is the English-translated version of 纳米技术 晶圆级纳米尺度相变存储单元电学操作参数测试规范.

GB/T 33657-2017 is the wafer level test specification for the electrical operating parameters of nano-scale phase change memory cells. The results can be used to characterize the electrical operability of a phase change material or device.

It applies to cells whose main raw material is a sulfur-based compound and whose electrode size, made by a semiconductor wafer process, is below 100 nm; cells from 100 nm to 300 nm may refer to it, and it does not apply to storage units that contain peripheral drive circuits.

It defines the phase change memory unit and the write, wipe and read operations, then covers the test equipment, the test sample structure, the selection of the test parameters, the test flow and the test report. It was issued on 12 May 2017 and has applied since 1 December 2017.

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Document preview — GB/T 33657-2017

National Standard of the People's Republic of China

ICS
31.200
Classification
L 56

Issued by: State Administration for Market Regulation; Standardization Administration of the PRC

Contents

  • Preface
  • Introduction
  • 1 Scope
  • 2 normative reference document
  • 3 Terms and definitions
  • 4 test equipment and equipment
  • 5 Test sample structure
  • Selection of test parameters
  • 7 Test Flow
  • 8 Test Report
  • Appendix A (informative) Construction of phase change memory unit test system
  • Appendix B (informative) Initialization method for phase change memory cells

Foreword

This standard is drafted in accordance with the rules given in GB/T 1.1-2009.

Introduction

Phase change memory is a nonvolatile memory whose memory cell can be used in the high impedance of the amorphous state under the thermodynamics of the external electric field Low resistance between the polycrystalline high-speed reversible structure changes, changes in resistance before and after the difference of up to 10 times, in order to achieve data storage Features.

The electrical operating parameters of the phase change memory cell include write operating parameters and wiping operating parameters. These parameters can be tested by this standard Standardize accurate extraction. They can not only effectively evaluate several performance indicators of phase change memory consisting of phase change memory cells, but also Phase change memory drive circuit, readout circuit and storage array design basis.

Phase change memory cells can be used in a wide range of phase change materials, the device structure can be achieved is not unique. The test specifications of this standard can be The performance characterization of different phase change materials and different phase change unit structures and the monitoring of process stability during phase change memory production For effective means.

As the operating current and phase change memory cell electrode size close relationship, too large electrode size will lead to operating current and power consumption surge, The corresponding electrical operating parameters test specifications may also exceed the scope of this standard. Specific to this standard, we develop suitable for use in memory Phase change memory cell with an electrode scale of less than 100 nm, and a phase change memory cell of 100 nm to 300 nm can also be executed with reference to this standard.

1 Scope

This standard specifies the wafer test specification for read and write parameters of nanoscale phase change memory cells. The test results can be used to characterize phase change The electrical operability of the storage material or device.

This standard applies to the sulfur-based compounds as the main raw material, based on semiconductor wafer manufacturing process electrode size is less than 100nm Of the phase change memory cell, 100nm ~ 300nm phase change memory cell can also refer to the implementation of this standard.

This standard does not apply to storage units that contain peripheral drive circuits.

2 Normative reference documents

The following documents are indispensable for the application of this document. For dated references, only the dated edition applies to this document. For undated references, the latest edition (including all modifications) applies to this document.

GB 4793.1-2007 Safety requirements for electrical equipment for measurement, control and laboratory use - Part 1: General requirements (IEC 61010-1:2001, IDT)

GB/T 9178 Integrated Circuit Terms

GB/T 11464 terminology for electronic measuring instruments

GB/T 13970 Basic terms of digital instrumentation

GB/T 13978 Digital Multimeter

3 Terms and definitions

GB/T 9178, GB/T 11464, GB/T 13970 and GB/T 13978 and the following terms and definitions apply to this file.

3.1 Phase change memory unit

A memory device capable of reversibly structuring a change between a polycrystalline phase and an amorphous phase under the thermodynamics of an external electric field unit.

3.2 Write operation

Phase change memory cell in the external electric field from the polycrystalline transition to amorphous process.

3.3 Wipe operation

Phase change storage unit in the role of external electric field from amorphous to polycrystalline process.

3.4 Read operation

By measuring the storage state of the resistance readout unit of the phase change memory cell.

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This preview omits tables, figures, formulas and parts of the technical clauses. The complete document — 15 pages — is available in the English PDF.

Referenced standards

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