GB/T 15879.620-2026Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ) (English PDF)

Foreword

This document complies with the provisions of GB/T 1.1-2020 "Standardization Work Guidelines Part 1: Structure and Drafting Rules of Standardization Documents".

Drafting.

This document is Part 6-20 of GB/T 15879 "Mechanical Standardization of Semiconductor Devices". GB/T 15879 has been published as follows.

part.

---Part 4: Classification and Coding System of Semiconductor Device Package Shapes;

---Part 5: Recommended values for tape-based automated bonding (TAB) of integrated circuits;

---Part 6-3.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Dimensions of Quad Flat Packages (QFP) Measurement methods;

---Part 6-4.General Rules for Drawing Outline Diagrams of Surface Mount Semiconductor Device Packages Ball Array (BGA) Package Dimensions

---Part 6-12.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Close-Pitch Pad Array Packages (FLGA) Design Guidelines;

---Part 6-13.Top Open Sockets for Close Pitch Ball Array Packages (FBGA) and Close Pitch Pad Array Packages (FLGA) Design guidelines;

---Parts 6-16.Ball Array Package (BGA), Pad Array Package (LGA), Close Pitch Ball Array Package (FBGA), and Close Pitch Ball Array Package (FBGA) Glossary of semiconductor testing and aging sockets for pitch pad array packages (FLGA);

---Part 6-18.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Ball Array Package (BGA) Design guide;

---Part 6-20.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Small Outline J-Pack (SOJ) Dimension measurement methods.

This document is equivalent to IEC 60191-6-20:2010 "Semiconductor devices – Mechanical standardization – Part 6-20.Surface mount semiconductors".

General rules for drawing device package outlines and methods for measuring the dimensions of small SOJ (Solitaire-Jet) packages.

The following minimal editorial changes have been made to this document.

---Added supplementary explanatory notes (see notes in Figures 1, 6, 7, 8, and 9, and note 4.5.2).

Please note that some content in this document may involve patents. The issuing organization of this document assumes no responsibility for identifying patents.

This document was proposed by the Ministry of Industry and Information Technology of the People's Republic of China.

This document is under the jurisdiction of the National Integrated Circuit Standardization Technical Committee (SAC/TC599).

Introduction

GB/T 15879 "Mechanical Standardization of Semiconductor Devices" mainly includes dimensional symbols and definitions for drawing semiconductor device outlines, and drawings.

Drawing rules, package shape classification and coding system, as well as standard outline drawings and recommended size ranges for various semiconductor device standard packages, etc.

The content is planned to consist of 23 parts.

---Part 1: General Rules for Drawing Discrete Device Outlines. The purpose is to define the dimensional symbols used for drawing outlines of semiconductor discrete devices.

And definitions, drawing rules, and instances, etc.

---Part 2: Dimensions. This section specifies the dimensional requirements for various semiconductor device packages.

---Part 3: General Rules for Drawing Integrated Circuit Outlines. The purpose is to define the dimension symbol codes and...

Definitions, drawing rules, and instances, etc.

---Part 4: Classification and Coding System for Semiconductor Device Package Shapes. The purpose is to define the classification of semiconductor device package shapes.

Class, model naming and coding system.

---Part 5: Recommended values for automated tape-on-board (TAB) bonding of integrated circuits. The purpose is to specify the recommended values for automated tape-on-board (TAB) bonding of integrated circuits.

Recommended package dimensions for the product.

---Part 6: General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages. The purpose is to specify the requirements for surface mount semiconductor...

General requirements and rules for drawing device package outlines.

---Part 6-1.General Rules for Drawing Surface Mount Semiconductor Device Package Outlines. Airfoil Lead Design Guidelines. Purpose it specifies the standard shape drawing, dimensions, and recommended range values for the airfoil lead-out end.

---Part 6-2.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages (Sections 1.50mm, 1.27mm, 1.00mm) Standard outline, dimensions, and recommended range values for pillar array packages.

---Part 6-3.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Dimensions of Quad Flat Packages (QFP) Measurement methods. The purpose is to define the measurement methods for the dimensions of Quad Flat Packages (QFP).

---Part 6-4.General Rules for Drawing Outline Diagrams of Surface Mount Semiconductor Device Packages Ball Array (BGA) Package Dimensions Measurement methods. The purpose is to specify the measurement methods for ball array (BGA) package dimensions.

---Part 6-5.General Rules for Drawing Surface Mount Semiconductor Device Package Outlines - Close-Pitch Ball Arrays (FBGAs) Design guidelines. The purpose is to specify the standard outline, dimensions, and recommended range values for close-pitch ball arrays (FBGAs).

---Part 6-6.General Rules for Drawing Surface Mount Semiconductor Device Package Outlines - Close Pitch Pad Array (FLGA) Design guidelines. The purpose is to specify the standard outline, dimensions, and recommended range values for square close-pitch pad arrays (FLGA).

---Parts 6-8.General Rules for Drawing Outlines of Surface Mount Semiconductor Device Packages Glass-Sealed Ceramic Quad Flat Packages (G-QFP) Design Guidelines. The purpose is to specify the standard outline and dimensions of the glass-sealed ceramic quad flat package (G-QFP).

Inches and recommended range values.

---Parts 6-10.General Rules for Drawing Outline Diagrams of Surface Mount Semiconductor Device Packages (Plastic is very thin, small outline, no leads) the dimensions of the P-VSON package. The purpose is to define the standard form factor for a very thin, small, leadless plastic P-VSON package.

Figure, dimensions, and recommended range values.

---Part 6-12.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Close-Pitch Pad Array Packages the design guidelines for Fine Pitch Array (FLGA) packages aim to specify the standard outline, dimensions, and push-out parameters for Fine Pitch Array (FLGA) packages.

Recommended range values.

---Parts 6-13.Top Open Sockets for Close Pitch Ball Array Packages (FBGA) and Close Pitch Pad Array Packages (FLGA) Standard outline, dimensions, and recommended range values for open sockets.

---Parts 6-16.Ball Array Package (BGA), Pad Array Package (LGA), Close Pitch Ball Array Package (FBGA), and Close Pitch Ball Array Package (FBGA) Glossary of semiconductor testing and aging sockets for pitch pad array packages (FLGA). The purpose is to define the terminology for ball array packages.

(BGA), LGA, FBGA, and FLGA Semiconductor testing and aging socket terminology and definitions.

---Part 6-17.General Rules for Drawing Surface Mount Semiconductor Device Package Outlines - Stack-up Package Design Guidelines - Close Pitch Ball Array Package (FBGA) and Close Pitch Pad Array Package (FLGA). The purpose is to define the Close Pitch Ball Array Package.

Standard outlines, dimensions, and recommended range values for (FBGA) and close pitch pad array (FLGA) packages.

---Part 6-18.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Ball Array Package (BGA) Design Guidelines. The purpose is to specify the standard outline, dimensions, and recommended range values for ball array packages (BGA).

---Part 6-19.Measurement methods and maximum permissible warpage of packages at high temperatures. The purpose is to specify the measures for package warpage at high temperatures.

Methods for measuring curvature and maximum permissible warp.

---Part 6-20.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Small Outline J-Pack (SOJ) Dimensional measurement methods. The purpose is to define the dimensional measurement methods for Small Outline J-Lead Packages (SOJ).

---Part 6-21.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages; Small Outline Package (SOP) Dimension Measurement Methodology. The purpose is to define a method for measuring the dimensions of small outline packages (SOPs).

---Part 6-22.General Rules for Drawing Outline Diagrams of Surface Mount Semiconductor Device Packages (S-) Design guidelines for FBGA (Silicon-Dense Pitch Array of Bonded Pads) and S-FLGA (Silicon-Dense Pitch Array of Bonded Pads) packages. The purpose is to specify the design requirements for silicon-dense pitch pad array packages.

Standard outlines, dimensions, and recommended range values for S-FBGA and S-FLGA packages.

Parts 6-20.Surface Mount Semiconductor Device Packaging General rules for drawing outline drawings Small Outline J-Lead Package (SOJ) Dimension Measurement Method

1 Scope

This document describes the dimensional measurements of the Small Outline J-Type Leaded Package (SOJ) conforming to IEC 60191-4 package outline classification E.

method.

2 Normative references

The contents of the following documents, through normative references within the text, constitute essential provisions of this document. Dated citations are not included.

For references to documents, only the version corresponding to that date applies to this document; for undated references, the latest version (including all amendments) applies.

This document.

IEC 60191-4 Mechanical standardization of semiconductor devices – Part 4: Classification and coding system for semiconductor device package shapes (Me-Note. GB/T 15879.4-2019 Mechanical Standardization of Semiconductor Devices Part 4: Classification and Coding System for Semiconductor Device Package Shapes (IEC 60191-4:2013, IDT) IEC 60191-6 Mechanical standardization of semiconductor devices – Part 6: General principles for drawing the outline of surface mount semiconductor devices packages

3 Terms and Definitions

The terms and definitions defined in IEC 60191-6 apply to this document.

4 Measurement Methods