GB/T 15879.4-2019Mechanical standardization of semiconductor devices -- Part 4: Coding system and classification into forms of package outlines for semiconductor device packages (English PDF)
半导体器件的机械标准化 第4部分:半导体器件封装外形的分类和编码体系
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Issued by
State Administration for Market Regulation, China National Standardization Administration
Level / Type
National · Recommended
Issue date
August 30, 2019
Implementation date
December 1, 2019
Scope
GB/T 15879.4-2019 is the English-translated version of 半导体器件的机械标准化 第4部分:半导体器件封装外形的分类和编码体系.
GB/T 15879.4-2019 — This part of GB/T 15879 specifies the classification and naming methods for the package shape of semiconductor devices, as well as packaging for semiconductor devices.
A systematic approach to general descriptive naming. This descriptive naming method provides a useful communication tool, but does not ensure that the same encoded package is interchangeable.
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Document preview — GB/T 15879.4-2019
National Standard of the People's Republic of China
- ICS
- 31.080
- Classification
- L 55
Issued by: State Administration for Market Regulation, China National Standardization Administration
Contents
- Foreword
- 1 Scope
- 2 coding system for semiconductor device package outline
- 3 Classification of semiconductor device package outlines
- 4 coding system for semiconductor device package
- 4.1 General
Foreword
GB/T 15879 "Mechanical Standardization of Semiconductor Devices" has been or is planned to be released as follows.
--- Part 1. General rules for drawing outlines of discrete device packages;
--- Part 2. Size;
--- Part 3. General rules for drawing outline drawings of integrated circuits;
--- Part 4. Classification and coding system for the outline of semiconductor device packages;
---Part 5. Recommended values for automated tape carrier integrated soldering (TAB);
--- Part 6. General rules for drawing outlines of surface mount semiconductor device packages.
This part is the fourth part of GB/T 15879.
This part is drafted in accordance with the rules given in GB/T 1.1-2009.
This section uses the translation method equivalent to IEC 60191-4.2013 "Mechanical standardization of semiconductor devices Part 4. Semiconductor devices
Classification and coding system for package shapes.
1 Scope
This part of GB/T 15879 specifies the classification and naming methods for the package shape of semiconductor devices, as well as packaging for semiconductor devices.
A systematic approach to general descriptive naming.
This descriptive naming method provides a useful communication tool, but does not ensure that the same encoded package is interchangeable.
2 coding system for semiconductor device package outline
The coding scheme for the following semiconductor device package outlines is applicable to the relevant mechanical drawings and documents.
a) Part 1. A three-digit serial number (000~999) indicating the numbering sequence;
b) Part II. a single letter representing the outline drawing (see Chapter 3);
c) Part III. Represents a two-digit serial number derived from the outline drawing (00~99).
The prefix P represents a temporary figure number.
Example.
---101A00;
---050G13;
---P101F01.
3 Classification of semiconductor device package outlines
The classification rules for the outline of semiconductor device packages are as follows.
a) Form A. single-ended lead;
b) Form B. heat sink installation;
c) Form C. bolt mounting;
d) Form D. axial lead;
e) Form E. surface mounting;
f) Form F. single-ended heat sink installation;
g) Form G. double column and four columns;
h) Form H. No lead in the axial direction.
4 coding system for semiconductor device package
4.1 General
A standard coding system is a method of identifying the physical characteristics of a semiconductor device package. The coding system contains at least two representation packages
Shape type letters. The coding system can be extended by optional parts, and the user can select as needed to provide additional package information.
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This preview omits tables, figures, formulas and parts of the technical clauses. The complete document — 30 pages — is available in the English PDF.
Referenced standards
Cited by
- GB/T 15879.620-2026Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)
- GB/T 15879.612-2025Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guidelines for fine-pitch land grid array (FLGA)
- GB/T 7092-2021Outline dimensions of semiconductor integrated circuits
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Related Standards
GB/T 15879.5-2018 — Mechanical standardization of semiconductor devices -- Part 5: Recommendations applying to tape automated bonding (TAB) of integrated circuits
GB/T 15879.603-2026 — Mechanical standardization of semiconductor devices - Part 6-3: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of quad flat packs (QFP)
GB/T 15879.604-2023 — Mechanical standardization of semiconductor devices - Part 6-4: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of ball grid array (BGA)
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