GB/T 15879.5-2018Mechanical standardization of semiconductor devices -- Part 5: Recommendations applying to tape automated bonding (TAB) of integrated circuits (English PDF)

Foreword

The Mechanical Standardization of Semiconductor Devices has been or is planned to be released as follows.

--- Part 1. General rules for drawing outlines of discrete device packages;

--- Part 2. Size;

--- Part 3. General rules for the drawing of outline drawings of integrated circuits;

--- Part 4. Classification and coding system for the outline of semiconductor device packages;

---Part 5. Recommended values for automated tape carrier integrated soldering (TAB);

--- Part 6. General rules for drawing outlines of surface mount semiconductor device packages.

This part is the fifth part of "Mechanical Standardization of Semiconductor Devices".

This part uses the translation method equivalent to IEC 60191-5.1997 "Mechanical standardization of semiconductor devices Part 5. Using carrier tapes

Recommended values for integrated circuit packages for dynamic soldering (TAB).

This part is drafted in accordance with the rules given in GB/T 1.1-2009.

This part replaces GB/T 15879-1995 "Mechanical standardization of semiconductor devices - Part 5.

(TAB) recommended value. Compared with GB/T 15879-1995, the main technical changes are as follows.

--- Increase in the scope "This section applies to the finished unit of the manufacturer to supply the user, the interconnection of the integrated circuit (IC) to the frame (introduction

Wire welding) is not explicitly required" (see Chapter 1);

---Remove the terms of guide hole, inner lead soldering, outer lead soldering, isolation strip, lead, sliding carrier, cutting, lead forming, etc.

Wheel holes, inner leads, outer leads or cut windows, support rings, body dimensions, outer leads, alignment holes, test pads, etc. (see

Chapter 2, version 2.2 of the.1995 edition;

---The carrier tape width is changed from "8mm, 16mm, 19mm, 35mm" (see 3.1 in GB/T 15879-1995) to "35mm,

48mm and 70mm" (see 4.1, 3.1 of the.1995 edition);

--- Increase the size and tolerances associated with film specifications, alignment holes, body dimensions and tolerances, pad patterns related dimensions and tolerances, external references

Line pitch related dimensions and tolerances, maximum number of lead combinations (see Chapter 4);

--- Increase the variable combination code (see Chapter 5);

--- Increase the internal and external lead welding requirements (see Chapter 6);

--- Increase the recommended value of ultra-large TAB package, wide body TAB package recommended value, outer lead number, test pad number (see this section)

Appendix A, Appendix B, Appendix C, Appendix D).

This section has the following editorial changes.

---Modified standard name;

--- Modified the error in the header of Table 2, the body size identification letters from A, B, C, D, F, G, H, J, K, corrected to A, B, C,

D, E, F, G, H, J, K;

--- Modified the error in the header of Table 5, the number of test pads in the header of Table 5 are all M1, according to the film specifications, test pad pitch

The difference is M1, M2, M3, M4;

---Modify the error in Table A.1, correct the outer lead pitch of BB-26 from 0.4mm to 0.15mm, and BB-36 from 0.4mm.

Positive 0.15mm, BD-46 is corrected from 0.16mm to 0.15mm;

--- Appendix B removes the completely repeated EH-46, and the wrong size EJ-46 of the body size (40mm x 40mm).

This part was proposed by the Ministry of Industry and Information Technology of the People's Republic of China.

This part is under the jurisdiction of the National Semiconductor Device Standardization Technical Committee (SAC/TC78).

This section drafted by. China Electronics Technology Standardization Institute, China Electronics Technology Group Corporation, 58th Institute, Sichuan Jiejie

General Electric Co., Ltd.

1 Scope

This part of the "Mechanical Standardization of Semiconductor Devices" specifies the use of tape automated bonding (TAB) as the main component of the structure and interconnection.

Recommended values for integrated circuit packages.

This section applies to the finished unit supplied by the manufacturer to the user. The interconnection of the integrated circuit (IC) to the carrier tape (internal lead soldering) is not clear.

Claim.

2 Terms and definitions

The following terms and definitions apply to this document.

2.1

Chip (or die) chip(ordie)

At least one integrated circuit is included from a silicon wafer containing an array of devices.

2.2

Tape carrier tapecarrier(tape)

A strip of mechanical support and electrical connection of the chip formed by laminating an insulating material and a conductive material having a certain pattern. Strip pack

Contains a series of graphics, each of which is a unit of the strip.

Note. When there is no confusion, the "band carrier" can be abbreviated as "carrier tape".

2.3

Chain gear hole sprockethole

The carrier carries a row of side holes on each side, through which the device transports the carrier tape, or for coarse adjustment of the carrier tape position.

2.4

Lead pattern leadpattern

After etching, the carrier tape has conductive material patterns including inner and outer leads and test pads.

2.5

Inner lead innerlead

The innermost conductor of the lead pattern connected to the chip.

2.6

Device window

Located in the center of the carrier unit, the chip and inner leads are placed in the holes.

2.7

Outer lead or cut window outerleadorexcisewindow

Each side of the carrier unit is suspended from a rectangular hole above the conductor pattern. These holes will form a continuous opening around each unit of the carrier tape.

mouth. The bonded circuit is typically cut away from the carrier tape in the opening.

2.8

Support ring

An insulating film that supports the conductor pattern between the device window and the outer lead window.

2.9

Body size bodysize

The outer dimensions of the support ring.

2.10

Outer lead outerlead

The outermost end of the lead pattern conductor connected to the next stage assembly after the soldered integrated circuit is cut and separated from the carrier tape.

2.11

Alignment hole alignmentholes

Auxiliary holes on the polymer film for carrier tape positioning during inner lead soldering, electrical testing and aging, cutting, and outer lead soldering.

2.12

Test pad testpads

A portion of the conductor pattern used to make electrical connections during live charging tests and aging tests.

3 Description of automatic tape welding (TAB)

Carrier tape automatic soldering is an integrated circuit assembly process for bare chips without conventional packages. The basic principle is to put each silicon core

The sheet is glued to a special flexible carrier tape. The carrier tape is composed of a thin plastic substrate on which a metal conductor is formed, like a flexible printed circuit.

At the inner end of the conductor, the lead pattern has a pattern that matches the solder joint of the chip. At the outermost end of the conductor, due to electrical testing of each conductor and

The solder joint has temporary contact. Between the chip connection solder joint and the test pad distribution, there is a long conductor without the support of the insulating film, which will eventually form.

The outer leads of the TAB package. The carrier tape, like film, has a row on each side of the carrier tape that is used in the assembly process to make it easy to transport.

Gear hole.

There are usually three main steps in the use of TAB carrier tape.

a) Inner lead soldering - soldering the integrated circuit chip to the lead terminals of the conductor on the carrier tape. The surface of the integrated circuit after soldering will be coated

The upper organic protective layer, or the entire integrated circuit, will be encapsulated.

b) Electrical test---The inner lead soldered chip can be electrically tested by the test pad provided by the carrier tape. Similar, integrated power

The road can be subjected to high temperature pretreatment or aging test.

c) External lead soldering - the integrated circuit is cut from the carrier tape and transferred to its final interconnect medium (printed circuit board or

On other substrates). The unsupported conductor remains after cutting, forming the outer leads of the TAB package. Outer leads and final

The substrate is soldered.

Manufacturers of TAB packages typically perform all of the functions required by steps a) and b). The user usually does what is required in step c)

Has a function. This section specifies the product format resulting from steps a) and b).

4 size requirements

This section specifies TAB variable parameters. film size, body size, test pad pitch, and outer lead pitch. Based on these four parameters will

The TAB size is composed of 4 groups, and each group has corresponding common conditions. All the size requirements in this section are shown in Table 1 to Table 4. Also includes four

A table of each possible maximum number of leads for a combination of parameters (see Table 5).

5 variable combination coding

Variables are numbered in UY-ZW format, U for membrane size, Y for body size, Z for test pad pitch, and W for external reference

Line pitch. The permissible values for each variable are specified as follows.

U=A, B or C corresponds to 35mm, 48mm or 70mm super large film, respectively, D or E corresponds to 48mm, 70mm width

Body type film.

Y=A, B, C, D, E, F, G, H, J or K correspond to 14mm x 14mm, 16mm x 16mm, 18mm x

18mm, 20mm x 20mm, 24mm x 24mm, 26mm x 26mm, 28mm x 28mm, 32mm x 32mm,

Square body size of 36 mm x 36 mm, 40 mm x 40 mm.

Note. The letter I is not used.

Z = 1, 2, 3 or 4 corresponds to a test pad pitch of 0.50 mm, 0.40 mm, 0.30 mm or 0.25 mm, respectively.

W=1, 2, 3, 4, 5 or 6 corresponds to 0.50 mm, 0.40 mm, 0.30 mm, 0.25 mm, 0.20 mm or 0.15 mm, respectively.

Outer lead pitch.

The combination of lead numbers in Table 5 specifies all 576 combinations of variables consisting of 4 major design parameters. Each variable combination consists of

4 identifiable parameter codes. Such as AA-22. the first A represents a super large membrane of 35mm width, and the second A represents

14mm x 14mm body size, the first 2 represents 0.40mm test pad pitch, the second 2 represents 0.40mm external reference

Line pitch. Similarly, the code CE-25 indicates. a very large film with a width of 70 mm, a body size of 24 mm x 24 mm, 0.40 mm

Test pad pitch, outer lead pitch of 0.20 mm. Table 5 lists all allowed membrane sizes and body size combinations, see 4.3.

6 Internal lead welding, external lead welding requirements (ILB and OLB)

The structure and size of the inner lead pattern cannot be specified in a specific way because the size of the integrated circuit on the chip and the land pattern are

Non-standardized.

Similarly, the shape and size of the outer leads after cutting separation and lead forming cannot be standardized because of the outer lead soldering process and the outer leads.

The molding process varies depending on the application.

a The form of these features is optional and may include the complete encapsulation or application of IC and other structures only on the top surface of the IC.

b When the viewing angle is one side of the metal conductor of the TAB package, W is the bottom surface of the support film.

Note. See from the side with the lead conductor.

Figure 1 Measurement reference and main matrix graphics

aD1 and E1 are package body sizes.

b D2 and E2 are the maximum allowable distances of the outer edges of the two outermost outer leads. Provide the necessary gap size from the outer lead range window to ensure cut

The feasibility of cutting the separation operation.

Note. See from the side with the lead conductor.

Figure 2 Body size and related tolerances

a These features may be formed by etching or punching a support film or etching a pattern on a metal layer. If etched metal alignment holes are used, the support film needs

Larger etch or punch to provide greater gaps in the metallized pattern. Corrosive metal alignment holes are recommended when there are tighter position tolerances (see

4.2).

b This size is for all test pads.

c This graphic is optional and does not require relying on carrier tape manufacturing techniques or application software.

Figure 3 Detail A

a These features provide a range for the outer lead cut on the support ring in production, or a "prohibited zone" for the wiring and outer leads, which is not mandatory. by

Due to the limitation of geometric size, these features cannot be used with AD-xx (35mm super large 20mmx20mm body size), BG-xx

(48mm super large 28mm x 28mm body size) and DG-xx (48mm wide body type 28mm x 28mm body size) variable series

Carrier tape.

b This graphic is optional and does not require relying on carrier tape manufacturing techniques or application software.

c These two features identify the first outer leads of the TAB package, which are only present at the corners shown in Figures 2 and 3. When the TAB package is placed in the sliding carrier

In time, the angle should correspond to a characteristic angle (usually chamfer) identifiable on the sliding carrier. The coding of the outer leads is only defined in the sub-assembly, any time

The positioning of the TAB package relative to the substrate is fixed (see Appendix C).

d D2 and E2 are the maximum allowable distances of the outer edges of the two outermost outer leads. Provide the necessary gap size from the outer lead range window to ensure cut

The feasibility of cutting the separation operation.

Figure 4 Detail B

a) Detail C (rotation 90°) d

b) Detail D (rotate 90°) d

a This feature identifies the center test pad on each side of the TAB package. The test pad is electrically connected to the outer leads and is used only for odd pads on each side.

(AD-xx, BG-xx and DG-xx).

b This size is for all test pads.

c The symbol "L" in the circle means. the positional tolerance that meets the minimum conditions allowed by the dimensional tolerance feature.

d According to the data of D(E) and D2(E2), all outer leads and test pads are evenly arranged.

Figure 5 details C and D

a) membrane alignment hole

b) metal alignment hole

Figure 6 Detail E

Appendix C

(informative appendix)

Outer lead number

C.1 When a TAB package is mounted on a substrate, it may be any of the four structures shown in Figure C.1, depending on the chip.

And the relative position of the carrier tape and the substrate. Device manufacturers may not know which direction is being used for any particular application, and some directions exist

Mirror relationship. For the above reasons, a convenient method for identifying the first outer lead and calculating the number of leads should be established.

C.2 TAB Package The first outer lead is defined by the positioning mark at one corner of the package body and is visible from each side of the package. This one

The corner identification mark consists of the lead thickened portion of the adjacent outer lead corners (see Figure C.2 and Figure C.4). When the TAB package is placed

When sliding in the carrier, the first outer lead angle corresponds to a identifiable characteristic angle (usually chamfered) on the sliding carrier (see Figure C.3).

The position of the first outer lead pattern determines where the lead number starts. When the package body is mounted on the substrate, the first outer lead is fixed

The corners are adjacent and numbered in a counterclockwise direction. The leads are numbered consecutively around the body in a counterclockwise direction (see Figure C.4). Counterclockwise numbering method

Consistent with lead numbering systems for other surface mount technology packages.

C.3 The advantage of using this method is that the characteristic position of the first outer lead has only one shape regardless of the structure of the TAB package on the substrate.

In this way, all packages on the substrate will follow the same numbering. In this way, the substrate designer can use a common and consistent padding

No. However, for a given device, the polyimide is facing up and the polyimide is facing down. There will be different leads for device functional relationships.

Numbered because they are mirror images of each other. Therefore, the device manufacturer has prepared two lead numbering methods according to the functional relationship between the chip and the carrier tape.

When the device is designed in a TAB package, the user should use it with care to ensure proper functionality.

a) b)

c) d)

Figure C.1 Location of the TAB package to the substrate

Figure C.2 1st outer lead po...