GB/T 15879.612-2025Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guidelines for fine-pitch land grid array (FLGA) (English PDF)

Foreword

This document complies with the provisions of GB/T 1.1-2020 "Standardization Work Guidelines Part 1: Structure and Drafting Rules of Standardization Documents".

Drafting.

This document is Part 6-12 of GB/T 15879 "Mechanical Standardization of Semiconductor Devices". GB/T 15879 has published the following...

part.

---Part 4: Classification and Coding System of Semiconductor Device Package Shapes;

---Part 5: Recommended values for tape-based automated bonding (TAB) of integrated circuits;

---Part 6-4.General Rules for Drawing Outline Diagrams of Surface Mount Semiconductor Device Packages Ball Array (BGA) Package Dimensions Measurement methods;

---Part 6-12.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Close-Pitch Pad Array Packages (FLGA) design guidelines.

This document is equivalent to IEC 60191-6-12:2011 "Semiconductor devices – Mechanical standardization – Part 6-12.Surface mount semiconductors".

General rules for drawing device package outlines. Design guidelines for close pitch pad array packages (FLGA).

Please note that some content in this document may involve patents. The issuing organization of this document assumes no responsibility for identifying patents.

The following minimal editorial changes have been made to this document.

---Added supplementary explanatory notes (see notes in Chapter 6, Figure 3, Figure 4, and Table 1);

---Added Appendix A (Informative). Outline diagram of FLGA plastic package with pads located inside the solder mask layer.

This document was proposed by the Ministry of Industry and Information Technology of the People's Republic of China.

This document is under the jurisdiction of the National Integrated Circuit Standardization Technical Committee (SAC/TC599).

Introduction

GB/T 15879 "Mechanical Standardization of Semiconductor Devices" is proposed to consist of 28 parts, corresponding to IEC 60191, mainly including...

Dimension symbols and definitions for semiconductor device outline drawings, drawing rules, package outline classification and coding system, and various types of semiconductor devices.

Outline drawing and recommended size range of the component package.

---Part 1: General Rules for Drawing Discrete Device Outlines. The purpose is to define the dimensional symbols used for drawing outlines of semiconductor discrete devices.

And definitions, drawing rules, and instances, etc.

---Part 2: Dimensions. This section specifies the dimensional requirements for various semiconductor device packages.

---Part 3: General Rules for Drawing Integrated Circuit Outlines. The purpose is to define the dimension symbol codes and...

Definitions, drawing rules, and instances, etc.

---Part 4: Classification and Coding System for Semiconductor Device Package Shapes. The purpose is to define the classification of semiconductor device package shapes.

Class, model naming and coding system.

---Part 5: Recommended values for automated tape-on-board (TAB) bonding of integrated circuits. The purpose is to specify the recommended values for automated tape-on-board (TAB) bonding of integrated circuits.

Recommended package dimensions for the product.

---Part 6: General Rules for Drawing Outlines of Surface Mount Semiconductor Devices. The purpose is to specify the outlines for surface mount semiconductor devices.

General requirements and rules for drawing package outline diagrams.

---Part 6-1.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages - Airfoil Lead Design Guidelines. The purpose is to...

The standard outline, dimensions, and recommended range values for the specified airfoil lead wires are provided.

---Part 6-2.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages 1.50mm, 1.27mm, 1.00mm Design guidelines for solder ball and post array packages with specific pitches. The aim is to specify solder ball and post array package design guidelines for 1.50mm, 1.27mm, and 1.00mm pitches.

Standard outlines, dimensions, and recommended range values for ball and pillar array packages.

---Part 6-3.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Dimensions of Quad Flat Packages (QFP) Measurement methods. The purpose is to define the measurement methods for the dimensions of Quad Flat Packages (QFP).

---Part 6-4.General Rules for Drawing Outline Diagrams of Surface Mount Semiconductor Device Packages Ball Array (BGA) Package Dimensions Measurement methods. The purpose is to specify the measurement methods for the external dimensions of ball array packages (BGA).

---Part 6-5.General Rules for Drawing Outlines of Surface Mount Semiconductor Devices Close Pitch Ball Array (FBGA) Design Guidelines South. The purpose is to specify the standard outline, dimensions, and recommended range values for close-pitch ball arrays (FBGA).

---Part 6-6.General Rules for Drawing Outlines of Surface Mount Semiconductor Devices - Design Guidelines for Close Pitch Array of Pads (FLGA) South. The purpose is to specify the standard outline, dimensions, and recommended range values for closely spaced grid pad arrays (FLGA).

---Parts 6-8.General Rules for Drawing Outline Diagrams of Surface Mount Semiconductor Device Packages Glass-Sealed Ceramic Quad Flat Packages (G-QFP) Design Guidelines. The purpose is to specify the standard outline and dimensions of the glass-sealed ceramic quad flat package (G-QFP).

Inches and recommended range values.

---Parts 6-10.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Thin Plastic, Small Outline, Leadless Packages the dimensions of (P-VSON) are specified. The purpose is to define the standard outline and dimensions of the very thin, small-form-factor, leadless plastic package (P-VSON).

Inches and recommended range values.

---Part 6-12.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Close-Pitch Pad Array Packages the design guidelines for Fine Pitch Array (FLGA) packages aim to specify the standard outline, dimensions, and push-out parameters for Fine Pitch Array (FLGA) packages.

Recommended range values.

---Parts 6-13.Top Open Sockets for Close Pitch Ball Array Packages (FBGA) and Close Pitch Pad Array Packages (FLGA) the design guidelines aim to specify the top-end specifications for close-pitch ball array packages (FBGA) and close-pitch pad array packages (FLGA).

Standard outline drawing, dimensions, and recommended range values for open fixtures.

---Parts 6-16.Ball Array Package (BGA), Pad Array Package (LGA), Close Pitch Ball Array Package (FBGA), and Close Pitch Ball Array Package (FBGA) Glossary of semiconductor testing and aging sockets for pitch pad array packages (FLGA). The purpose is to define the terminology for ball array packages.

(BGA), LGA, FBGA, and FLGA.

Semiconductor testing and aging fixture terminology definitions.

---Part 6-17.General Rules for Drawing Surface Mount Semiconductor Device Package Outlines - Stack-up Package Design Guidelines - Close Pitch Ball Array Package (FBGA) and Close Pitch Pad Array Package (FLGA). The purpose is to define the Close Pitch Ball Array Package.

Standard outlines, dimensions, and recommended range values for (FBGA) and close pitch pad array (FLGA) packages.

---Part 6-18.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Ball Array Package (BGA) Design Guidelines. The purpose is to specify the standard outline, dimensions, and recommended range values for ball array packages (BGA).

---Part 6-19.Measurement methods and maximum permissible warpage for packaged surfaces at high temperatures. The purpose is to specify the warpage of packages at high temperatures.

And the method for measuring the maximum permissible warpage size.

---Part 6-20.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages Small Outline J-Pack (SOJ) Dimensional measurement methods. The purpose is to define the dimensional measurement methods for J-lead small outline packages (SOJ).

---Part 6-21.General Rules for Drawing Outline Drawings of Surface Mount Semiconductor Device Packages; Small Outline Package (SOP) Dimension Measurement Methodology. The purpose is to define the method for measuring the dimensions of small outline packages (SOPs).

---Part 6-22.General Rules for Drawing Outline Diagrams of Surface Mount Semiconductor Device Packages Silicon Dense Pitch Ball Array Packages Design guidelines for Silicon-Dense Pitch Array (S-FBGA) and Silicon-Flat-Pitch Array (S-FLGA) packages. The purpose is to specify the design of silicon-dense pitch pad arrays.

Standard outlines, dimensions, and recommended ranges for Array Layout Package (S-FBGA) and Silicon Dense Pitch Pad Array Package (S-FLGA).

Mechanical standardization of semiconductor devices Parts 6-12.Surface Mount Semiconductor Device Packaging General rules for drawing outline diagrams of close-pitch pad arrays Column Package (FLGA) Design Guide

1 Scope

This document provides the standard outline, dimensions, and specifications for close-pitch pad array packages (FLGA) with a lead pitch of 0.80 mm or less.

Recommended range of values.

2 Normative references

The contents of the following documents, through normative references within the text, constitute essential provisions of this document. Dated citations are not included.

For references to documents, only the version corresponding to that date applies to this document; for undated references, the latest version (including all amendments) applies.

This document.

devices)

Note. GB/T 15879.4-2019 Mechanical Standardization of Semiconductor Devices Part 4: Classification and Coding System for Semiconductor Device Package Shapes (IEC 60191-4:2013, IDT) GB/T 15879.5-2018 Mechanical standardization of semiconductor devices - Part 5: Recommended values for tape-based automated bonding (TAB) of integrated circuits (IEC 60191-5:1997, IDT) GB/T 15879.604-2023 Mechanical standardization of semiconductor devices – Part 6-4.Drawing of package outlines for surface mount semiconductor devices Dimensional measurement method for general ball array (BGA) packages (IEC 60191-6-4:2003, IDT)

3 Terms and Definitions

The terms and definitions defined in IEC 60191 (all parts) and the following terms and definitions apply to this document.

fine-pitchlandgridarray the package has at least three rows and three columns of metal pads with a pitch of 0.80 mm or less on one side of the substrate, wherein the metal pads the maximum height is no more than 0.10mm.

Note. Some row and column intersections may not have leader lines.

Flange-type FLGA

FLGA is a package whose shape (length, width) is defined by the flange shape (in most cases, the shape of the substrate) that extends beyond the substrate or flip chip.

Note. As shown in Figure 1, flanges are usually made by stamping, so their dimensional error is larger than that of cutting.