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GB/T 48178-2026Testing method for integrated circuit electronic design automation tools (English PDF)

集成电路电子设计自动化工具测试方法

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Issued by

SAMR; SAC

Level / Type

National · Recommended

Issue date

August 28, 2026

Implementation date

March 1, 2027

Scope

GB/T 48178-2026 is the English-translated version of 集成电路电子设计自动化工具测试方法.

Electronic design automation tools are central to integrated circuit design, and errors in them can propagate into silicon. This document sets out a testing method for integrated circuit EDA tools, offering tool vendors and users a structured way of checking how such software behaves.

Likely readers are EDA software developers, semiconductor design houses that qualify the tools they depend on, independent test laboratories, and organisations that procure design software and need a basis for evaluation. Quality and verification managers in chip design teams may also find it useful. It is a recommended national standard, so it is voluntary unless invoked by contract or another rule. It was issued on 28 August 2026 and takes effect on 1 March 2027. It is an original Chinese document and does not adopt an international standard. Domestic chip design has grown quickly in China, and a common method for testing the tools involved supports fair comparison between products from different vendors.

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Document preview — GB/T 48178-2026

National Standard of the People's Republic of China

ICS
31.200
Classification
L55

Issued by: State Administration for Market Regulation; Standardization Administration of China

Contents

  • Foreword
  • 1 Scope
  • 2 Normative references
  • 3 Terms and definitions

Foreword

GB/T 48178-2026 is a recommended national standard (GB/T) of the People's Republic of China, issued on 28 August 2026 by the State Administration for Market Regulation and the Standardization Administration of China, with effect from 1 March 2027.

It is under the responsibility of the Ministry of Industry and Information Technology (Electronics).

Classification: ICS 31.200; CCS L55.

1 Scope

Electronic design automation tools are central to integrated circuit design, and errors in them can propagate into silicon. This document sets out a testing method for integrated circuit EDA tools, offering tool vendors and users a structured way of checking how such software behaves.

Likely readers are EDA software developers, semiconductor design houses that qualify the tools they depend on, independent test laboratories, and organisations that procure design software and need a basis for evaluation. Quality and verification managers in chip design teams may also find it useful. It is a recommended national standard, so it is voluntary unless invoked by contract or another rule. It was issued on 28 August 2026 and takes effect on 1 March 2027. It is an original Chinese document and does not adopt an international standard. Domestic chip design has grown quickly in China, and a common method for testing the tools involved supports fair comparison between products from different vendors.

Remaining clauses in the full document

  • 2 Normative references
  • 3 Terms and definitions

......
This preview omits tables, figures, formulas and parts of the technical clauses. The complete document — 31 pages — is available in the English PDF.

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