GB/T 44791-2024Integrated circuit 3D packaging—Requirement for bumping-wafer-thinning process and evaluation (English PDF)

集成电路三维封装带凸点圆片减薄工艺过程和评价要求

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Issued by

SAMR; SAC

Level / Type

National · Recommended

Issue date

October 26, 2024

Implementation date

May 1, 2025

Scope

GB/T 44791-2024 is the English-translated version of 集成电路三维封装带凸点圆片减薄工艺过程和评价要求.

GB/T 44791-2024 is the Chinese national standard covering the grinding that takes a bumped wafer down to stacking thickness — the equipment and the materials, the protective film applied over the bumps, the coarse grind, the fine grind and the optional polish, the cleaning, the UV release and the removal of the film, the labelling, packaging and records, and the evaluation of roughness and of the damaged layer left under the ground surface, which is what cracks later. Companion to the wafer sawing standard GB/T 44796-2024 and the die stacking standard GB/T 44775-2024. First edition, under the Ministry of Industry and Information Technology. In force from 1 May 2025. Issued on 26 October 2024, it has been in force since 1 May 2025.

Document preview — GB/T 44791-2024

National Standard of the People's Republic of China

ICS: 31.200
Classification: L 55

Issued by: State Administration for Market Regulation; Standardization Administration of the PRC

PrefaceIII
1 Scope1
2 Normative references1
3 Terms, Definitions and Abbreviations1
3.1 Terms and Definitions1
3.2 Abbreviations2
4 General Requirements2
4.1 Equipment, instruments and fixtures2
4.2 Materials3
4.3 Notes3
5 Detailed requirements3
5.1 Environment3
5.2 Typical process flow3
5.3 Process Preparation4
5.4 Applying protective film5
5.5 Coarse Grind5
5.6 Fine grinding5
5.7 Polishing (if necessary)6
5.8 Cleaning6
5.9 UV degumming (if necessary)6
5.10 Peel off the film6
5.11 Labelling, storage and transport6
5.12 Packaging7
5.13 Record7
6 Evaluation Requirements7
6.1 Evaluation requirements for film7
6.2 Evaluation requirements for thinning7
6.3 Evaluation requirements for cleaning8
6.4 Evaluation requirements for debonding and film removal8

Foreword

This document is in accordance with the provisions of GB/T 1.1-2020 "Guidelines for standardization work Part 1: Structure and drafting rules for standardization documents" Drafting.

Please note that some of the contents of this document may involve patents. The issuing organization of this document does not assume the responsibility for identifying patents.

This document is proposed by the Ministry of Industry and Information Technology of the People's Republic of China.

This document is under the jurisdiction of the National Technical Committee for Standardization of Integrated Circuits (SAC/TC599).

This document was drafted by the 58th Research Institute of China Electronics Technology Group Corporation and Shenzhou Loongson Intelligent Technology Co., Ltd.

The main drafters of this document are Yuan Shiwei, Wang Bo, Xiao Hanwu, Wang Yanting, Huang Hailin, Xiao Longteng, and Chen Mingmin.

Thinning process of wafer with bumps for integrated circuit 3D packaging Process and evaluation requirements

1 Scope

This document specifies the thinning process for 12-inch and below integrated circuit 3D packaging with bump wafers (hereinafter referred to as thinning process) Process and evaluation requirements.

This document is applicable to bumped wafers of 12 inches or less that need to be thinned. Note. 1 in = 2.54 cm.

2 Normative references

GB/T 25915.1-2021

3 Terms, definitions and abbreviations

3.1 Terms and Definitions

The following terms and definitions apply to this document.

3.1.1 Roughness

The micro-geometric characteristics of the thinned surface are composed of small spacing and peaks and valleys.

3.1.2 damaged layer

The outermost layer is a rough and broken surface structure, and the middle area is the cracks caused by the outermost layer and its cracks.

The inner part is composed of extended microcracks, and the inner part is the elastic deformation area extending from the microcrack extension area.

Note. The schematic diagram of the damaged layer is shown in Figure 1.

Figure 1 Schematic diagram of the damaged layer

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This preview omits tables, figures, formulas and parts of the technical clauses. The complete document — 15 pages — is available in the English PDF.

Referenced standards

Normative references

GB/T 25915.1-2021

Editions of GB/T 44791

Edition	Title	Revision	Status
GB/T 44791-2024	Integrated circuit 3D packaging - Requirement for bumping-wafer-thining process and evaluation	current edition	Current

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