GB/T 41033-2021Design requirements for radiation hardening of CMOS integrated circuits (English PDF)
CMOS集成电路抗辐射加固设计要求
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Issued by
SAMR; SAC
Level / Type
National · Recommended
Issue date
December 31, 2021
Implementation date
July 1, 2022
Scope
GB/T 41033-2021 is the English-translated version of CMOS集成电路抗辐射加固设计要求.
China's national design requirements for radiation hardening CMOS integrated circuits. Radiation damages a CMOS circuit in two distinct ways and hardening must address both. Total ionising dose accumulates over years: charge trapped in the oxides shifts transistor thresholds and increases leakage until the circuit no longer works, and it is a gradual, predictable ageing. Single event effects are instantaneous: one heavy ion passing through the silicon deposits enough charge to flip a memory bit, corrupt a logic state, or - worst - trigger the parasitic thyristor inherent in CMOS and latch the device into a short circuit that destroys it unless power is removed. The design remedies differ accordingly. Total dose is fought with process and layout, with enclosed transistor geometries and guard rings; single events with redundancy, with error correction, and with layout that separates the nodes that must not fail together.
Document preview — GB/T 41033-2021
National Standard of the People's Republic of China
- Classification
- V 29
Issued by: State Administration for Market Regulation; Standardization Administration of the PRC
Contents
- ForewordI
- 1 Scope1
- 2 Normative references1
- 3 Terms, Definitions and Abbreviations1
- 3:1 Terms and Definitions1
- 3:2 Abbreviations2
- 4 Design Process2
- 5 Radiation hardening design requirements3
- 5:1 Design principles and requirements for anti-total dose radiation reinforcement3
- 5:2 Design principles and requirements for anti-single-event radiation hardening7
- 6 Requirements for Modeling and Simulation of Radiation Effects of Integrated Circuits10
- 6:1 General Requirements for Modeling and Simulation of Radiation Effects of Integrated Circuits10
- 6:2 Requirements for Modeling and Simulation of Radiation Effects of Integrated Circuits10
- 6:3 Modeling and Simulation Methods for Radiation Effects of Integrated Circuits10
- 7 Irradiation verification test requirements11
- 7:1 Requirements for total dose irradiation verification test11
- 7:2 Single particle irradiation verification test requirements14
Foreword
This document is in accordance with the provisions of GB/T 1:1-2020 "Guidelines for Standardization Work Part 1: Structure and Drafting Rules of Standardization Documents" drafted:
Please note that some content of this document may be patented: The issuing agency of this document assumes no responsibility for identifying patents:
This document is proposed and managed by the National Standardization Technical Committee of Aerospace Technology and Its Application (SAC/TC425):
This document is drafted by: The No: 771 Research Institute of the Ninth Research Institute of China Aerospace Science and Technology Corporation:
The main drafters of this document: Liu Zhi, Ge Mei, Xie Chengmin, Wang Bin, Yu Hongbo, Yue Hongju, Yao Siyuan, Li Haisong, Geng Zengjian, Hu Qiaoyu:
Radiation hardening design requirements for CMOS integrated circuits
1 Scope
This document specifies the process, design requirements, modeling and simulation, verification and design of CMOS integrated circuits for radiation resistance (total dose, single event) hardening design:
verification test requirements:
This document applies to digital integrated circuits, analog integrated circuits and digital-analog hybrid integrated circuits based on bulk silicon/SOICMOS process:
Radiation-resistant (total dose, single particle) rugged design:
2 Normative references
The contents of the following documents constitute essential provisions of this document through normative references in the text: Among them, dated citations
documents, only the version corresponding to that date applies to this document: For undated references, the latest edition (including all amendments) applies to this document:
GB/T 9178 Integrated Circuit Terminology
3 Terms, Definitions and Abbreviations
3:1 Terms and Definitions
The terms and definitions defined in GB/T 9178 and the following apply to this document:
totalionizingdoseeffects; TID
The total dose radiation effect refers to the phenomenon that the accumulation of ionizing radiation leads to the degradation of the parameters of the device:
single event effects; SEE
A single heavy ion or proton with a certain energy is injected into the integrated circuit, causing the integrated circuit to flip, lock, burn, etc:, resulting in the integrated circuit
A general term for the phenomenon of performance degradation or functional failure:
singleeventupseteffects; SEU
Effects of changes in the logic state of integrated circuits induced by single-event radiation:
singleeventtransienteffects;SET
The effect of an abnormal pulse signal at the output of an integrated circuit caused by single-event radiation:
Single event latch-up effects; SEL
The effect of integrated circuit latch-up caused by single event radiation:
Design reinforcement radiationhardeningbydesign; RHBD
The technology of improving the radiation resistance of semiconductor devices or integrated circuits by designing circuit topology and layout structure with radiation resistance:
Remaining clauses in the full document
- 4 Design Process
- 5 Radiation hardening design requirements
- 6 Requirements for Modeling and Simulation of Radiation Effects of Integrated Circuits
- 7 Irradiation verification test requirements
......
This preview omits tables, figures, formulas and parts of the technical clauses. The complete document — 17 pages — is available in the English PDF.
Referenced standards
Normative references
GB/T 9178
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